Ing. Pavel Kubalík, Ph.D.

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10.1109/MECO62516.2024.10577851

Katedra číslicového návrhu

This paper is focused on neural network implementation on FPGA. Linearly approximated functions combined with quantization are used to efficiently implement neural networks in hardware. Famous benchmarks were used for learning, evaluation, and hardware testing. Approximation-aware and quantization-aware learning were used to obtain weights for neurons in hardware. We implemented a neural network with an 8-bit architecture in VHDL and synthesized it to Zynq FPGA in Vivado. The resulting design running at 100MHz clock frequency was carefully tested against hardware-accurate models written in Wolfram Mathematica and C++. We present a decrease in FPGA resources and chip utilization compared to 16-bit architecture implementation.

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10.1109/MECO58584.2023.10155065

Katedra číslicového návrhu

Integrating artificial intelligence technologies into embedded systems requires efficient implementation of neural networks in hardware. The paper presents a Zynq 7020 FPGA implementation and evaluation of a middle-sized dense neural network based on approximate computation by linearly approximated functions. Three famous benchmarks were used for classification accuracy evaluation and hardware testing. We use our highly pipelined neural hardware architecture that takes weights from block RAMs to save logic resources and enables their update from the processing system. The architecture reaches excellent design scalability, allowing us to estimate the number of neurons implemented in programmable logic based on single-neuron resources. We reached nearly full chip utilization while preserving the high clock frequency for the FPGA used.

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10.1109/MECO55406.2022.9797141

Katedra číslicového návrhu

Approximate arithmetic is a very important approach for implementing neural networks in embedded hardware. The requirements of real-time applications with respect to the size of deep neural networks force designers to simplify the neural processing elements. Not only the reduction of precision of model parameters to a few bits, but also the use of approximate arithmetic increases computational power and saves on-chip resources beyond exact computation. Since it was shown that linearly approximated functions are suitable for implementing neural networks in hardware, FPGAs have improved. So we decided to re-implement the processing element on a modern FPGA and to present implementation results regarding speed and resource consumption. A neural processing element based on linearly approximated functions was implemented in Vivado and tested on an xc7 FPGA. The results show that the architecture saves significant resources and a clock frequency above 100 MHz can be achieved in pipelined design.

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10.1109/ICECS202256217.2022.9970813

Katedra číslicového návrhu

This paper is focused on the feasibility of a neural network with linearly approximated functions on modern FPGA. An approximate multiplier and linearly approximated activation functions were used for a neural network implemented on Zynq FPGA. We proposed a novel architecture for a fully functional, layered, and configurable neural network.

Článek

10.1109/ACCESS.2020.3029691

Katedra číslicového návrhu

This paper presents a detailed analysis of various approaches to hardware implemented compression algorithm dictionaries, including our optimized method. To obtain comprehensive and detailed results, we introduced a method for the fair comparison of programmable hardware architectures to show the benefits of our approach from the perspective of logic resources, frequency, and latency. We compared two generally used methods with our optimized method, which was found to be more suitable for maintaining the memory content via (in)valid bits in any mid-density memory structures, which are implemented in programmable hardware such as FPGAs (Field Programmable Gate Array). The benefits of our new method based on a “Distributed Memory” technique are shown on a particular example of compression dictionary but the method is also suitable for another use cases requiring a fast (re-)initialization of the used memory structures before each run of an algorithm with minimum time and logic resources consumption. The performance evaluation of the respective approaches has been made in Xilinx ISE and Xilinx Vivado toolkits for the Virtex-7 FPGA family. However the proposed approach is compatible with 99% of modern FPGAs.

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10.1109/MECO49872.2020.9134348

Katedra číslicového návrhu
Fakulta informačních technologií

This paper describes the properties of wireless data transfer for Internet of Things (IoT). It focuses on low power consumption of the device. The paper presents the results of measuring latency, throughput and power consumption of a GSM module connected to an Arduino during data transfer to a remote server running at a PC. The measuring methodology of obtaining these results is discussed. Power consumption measurements include sending files of various sizes from the GSM module via the GSM network to the server. Conclusions regarding battery lifespan for the GSM module are made in the paper. Throughput over the GSM network for this module is elaborated and a static part of sending time, of a file regardless its size, is identified in this paper. The throughput is measured in order to further analyze the usability of such a device in IoT. The usability of LTE in such a configuration for fast data transfer is also discussed. The latency between the GSM module and the server is approximated because it may influence power consumption.

Článek

10.1002/navi.390

Katedra číslicového návrhu

This paper presents a new modified Single Block Zero-Padding (mSBZP) Partial Correlation Method (PCM) Parallel Code Search (PCS) algorithm for effective acquisition of weak GNSS tiered signal using coherent processing of its secondary code (SC) component. Two problems are discussed: acquisition of primary codes with longer period using FFT blocks of limited length, and the utilization of PCS in the presence of SC bit transition. The PCM and SC bit transition forms parasitic fragments in the Cross-Ambiguity-Function (CAF) to devaluate signal detection performance. A novel analysis of this mechanism and its impact is presented. A novel mSBZP-PCM-PCS algorithm is proposed, which does not degrade the CAF. Then, the algorithm is combined with SC bit transition removal schema and sequential search to construct an estimator for weak tiered signal acquisition. The performance of the method is demonstrated by analysis and computer simulation using Galileo E1C and GPS L1C-P signals.

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10.1109/CCWC.2019.8666521

Katedra číslicového návrhu

This paper presents an attempt to combine recent research in fields of hardware- and software-based high throughput universal lossless compression algorithms and their implementations, resulting into a case study focusing on one of the most critical parts of compression algorithms – a Match Search Unit (MSU) and its parallelization. The presented FPGA design combines ideas of the LZ4 algorithm (which is derived from the most common LZ77) with the state of the art hardware architectures for lossless compression also based on LZ77. This approach might lead to a smaller, better organized or more efficient ”building block” for modern implementations of hardware driven lossless compression algorithms. The presented design focuses on optimization of the main problem of the LZ77 family, namely the construction of and searching in a compression dictionary. Particularly, we combine a Live Value Table (LVT) with multi-ported memory in order to improve the bandwidth of the dictionary and the Fibonacci hashing principle originating from LZ4 algorithm to decrease latency of the MSU and to achieve overall higher throughput rate. For the design synthesis an FPGA of the Xilinx Virtex-7 family was used.

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10.1109/ReConFig48160.2019.8994794

Katedra číslicového návrhu

This paper presents an FPGA design implementing a single LZ4 lossless compression IP block, providing a throughput of 6 Gbps combined with extremely low latency, while still retaining full binary compatibility with the original LZ4 format. The best-known competitor is capable of processing up to 2 Gbps per block/engine with unknown latency. The presented design uses two key features: a low-latency 8-way match search unit and consequently a match buffer which allows encoding LZ4 sequences independently to reduce stalls in the data processing pipeline. The design was evaluated on several compression corpora with an average compression ratio of 1.7.

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10.1109/CCWC.2019.8666446

Katedra číslicového návrhu

This document presents a new approach to network jitter measurement and analysis in asynchronous data networks such as Ethernet. The developed monitoring device is capable to analyze an incoming stream speed of 1 Gb/s with the resolution up to 8 ns. The system architecture supports speeds up to 100 Gb/s networks. The presented architecture can provide several statistical functions such as measuring a network jitter by Interarrival Histograms method providing the mean value and peak-to-peak value as well. The architecture was implemented and tested on Xilinx Kintex UltraScale FPGA chip using Avnet AES-KU040-DB-G development board.

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10.1145/3174243.3174976

Katedra číslicového návrhu

This paper presents a performance comparison of various approaches of realization of status register suitable for maintaining (in)valid bits in mid-density memory structures implemented in Xilinx FPGAs. An example of a such structure with status register could be a dictionary for Lempel-Ziv based lossless compression algorithms where the dictionary has to be initialized before each run of the algorithm with minimum time and logic resources consumption. The performance evaluation of designs has been made in Xilinx ISE and Vivado toolkits for the Virtex-7 FPGA. This research has been partially supported by the CTU project SGS17/017/OHK3/1T/18 "Dependable and attack-resistant architectures for programmable devices" and by the project "E-infrastructure CESNET "modernization" no. CZ.02.1.01/0.0/0.0/16 013/0001797.

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Katedra číslicového návrhu

This contribution describes an architecture of additional system of memories for an existing GNSS (Global Navigation Satellite Systems) signal acquisition unit in frequency domain. The unit is designed for an FPGA-based HW receiver and has three 4K FFT blocks. The receiver is based on the System on Chip (SoC) Xilinx ZYNQ platform. The proposed additional memories are used as accumulators of complex signals samples and are placed in front or after the acquisition unit. They enable to process GNSS signals of different navigation systems more effectively with limited resources

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Katedra číslicového návrhu

The objective of this contribution is a design of optimal algorithms for an universal GNSS acquisition unit. The unit is designed for a FPGA-based HW receiver and is implemented in frequency domain with three 4K FFT blocks. The unit is able to acquire usual civil signals (GPS C/A, BeiDou B1, IRNSS L5/S-band, and GLONASS L1OF) directly and to acquire the Galileo E1 longer code signal with proposed improved algorithm of the partial correlation. Pre- and mainly post-correlation methods are analyzed and selected with respect to implementation on the target System on Chip (SoC) Xilinx ZYNQ platform with limited computing resources.

Článek

10.1007/s11265-016-1146-1

Katedra číslicového návrhu
Katedra počítačových systémů

This paper is focused on error-free solution of dense linear systems using residual arithmetic in hardware. The designed Modular System uses hardware identical Residual Processors (RP)s for solving independent systems of linear congruences and combines their solutions into the solution of the given linear system. This approach uses the residue number system which is based on the Chinese remainder theorem. In order to efficiently exploit parallel processing and cooperation of the individual components, a hardware architecture of the Modular System with several RPs is designed. In order to verify the proposed architecture, a Xilinx FPGA with a MicroBlaze processor was used. Experimental results are obtained for an evaluation FPGA board with Virtex 6. Results from implementation serve for subsequent theoretical analysis of the system performance for various linear system sizes and further improvement of the system. The proposed system can be useful as a special hardware peripheral or a part of an embedded system for solving large nonsingular systems of linear equations with integer, rational or floating-point coefficients with arbitrary precision.

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Katedra číslicového návrhu

The objective of this contribution is a design of universal GNSS acquisition unit for an FPGA-based HW receiver, which is able of direct acquisition of usual civil signals (GPS C/A, BeiDou B1, IRNSS L5/S-band, and GLONASS L1OF). Due to high complexity of calculation and requirements for latency, processing in frequency domain with parallel search in code is adopted. Optimal processing methods even for the long codes of Galileo E1 or future GPS L1C signals are analyzed. For each block of the acquisition unit, a method is selected with respect to implementation on the target System on Chip (SoC) Xilinx ZYNQ platform. The unit is intended as a HW acquisition accelerator with a minimal SW handling requirements for the developed receiver.

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10.1109/ReConFig.2016.7857146

Katedra číslicového návrhu

This paper describes analysis and implementation of a new method for maintaining valid content of FPGA memory blocks with an asymptotically constant time synchronous clear ability, that can be useful for (re)initialization to one default value. A particular application can be for high-speed real-time LZ77 lossless compression algorithms, where a dictionary has to be (re)initialized before each run of the implemented compression algorithm. The method is based on two most widely used techniques for clearing the memory content: a linear passage of the memory and clearing each cell by writing a default value and creating a register field providing an (in)valid bit for each memory cell. Our solution combines these two techniques together with the use of FPGA distributed memory blocks implemented in LUTs (Look-Up Tables) to overcome negative features of each previous method without losing the most of positive features. Our solution provides a balance between the two previous techniques and exceeds them in speed, resources utilization and latency of (re)initialization.

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Katedra číslicového návrhu
Katedra počítačových systémů

Tento článek se zabývá novým a efektivním způsobem zajištěná platnosti dat ve vestavných pamětech uvnitř FPGA, který je vhodný pro realizaci slovníků v bezztrátových kompresních algoritmech realizovaných v hardwaru (FPGA). Klíčem k této inovaci je chytré využití vlastností LUT (Look-Up Table), které umožňuje dosáhnout menšího počtu využitých zdrojů a vyšší frekvence celého systému oproti běžně používaným způsobům realizace. Tato metoda je navržena pro vysokou propustnost a nízkou latenci, což ji činí vhodnou pro kompresi jumbo IP packetů obsahující multimediální data v reálném čase. Použitou metodu je možné aplikovat na další datové struktury, které jsou mapovány do vestavných bloků RAM v FPGA.

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10.1109/ICECS.2015.7440278

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Katedra počítačových systémů

This paper describes analysis and implementation of a LZ4 compression algorithm. LZ4 is derived from a standard LZ77 compression algorithm and is focused on the compression and decompression speed. The LZ4 lossless compression algorithm was analyzed regarding its suitability for hardware implementation. The first step of this research is based on software implementation of LZ4 with regard to the future hardware implementation. As a second step, a simple hardware implementation of LZ4 is evaluated for bottlenecks in the original LZ4 code. Xilinx Virtex–6 and 7–Series FPGAs are used to obtain experimental results. These results are compared to the industry competitor.

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Katedra číslicového návrhu
Katedra počítačových systémů

Výzkum se zabývá bezztrátovým kompresním algoritmem LZ4 (založeném na LZ77) a jeho vhodnosti pro kompresi multimediálních dat a univerzální paketovou kompresi pro sít’ové spolupráce v reálném čase v oblastech citlivých na zpoždění.

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10.1109/ICECS.2014.7050083

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Katedra počítačových systémů

The paper describes an ASIC implementation of a linear congruence solver, part of a parallel system for solution of linear equations, and presents synthesis results for three different standard cell libraries. The previous VHDL design was adapted to three ASIC technologies (130 nm, 110 nm, and 55 nm) from two different vendors and the synthesized results were mutually compared. The comparison results were further used to obtain a view of design properties in higher density technologies.

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Katedra číslicového návrhu
Katedra počítačových systémů

The work is focused on design of a Modular System performing error-free solution of dense linear systems using residue arithmetic in Xilinx FPGA. The designed system shall use a set of Residual Processors (RP)s for linear system solution in Residue Number System and reconstruct the set's solution afterwards. The currently proposed system's architecture has a single RP, a large DDR memory used for data transfer in between a PC and the system, and a built-in MicroBlaze processor. Future work will focus on extending the architecture to implement the entire Modular System consisting of multiple RPs and performing the backward transformation from residue representation into the rational number set.

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10.1109/ISSOC.2014.6972445

Katedra číslicového návrhu
Katedra počítačových systémů

This paper is focused on hardware error-free solution of dense linear systems using residual arithmetic on a System on Chip Modular System. The designed Modular System uses Residual Processors (RP)s for solving independent linear systems in residue arithmetic and combines RP solutions into solution of the linear system. A System on Chip architecture of the Modular System with several RPs is designed, each with a large memory unit used for data transfer and storage. A Xilinx FPGA architecture with a MicroBlaze processor is used to verify the proposed architecture. The experimental results are obtained for an evaluation FPGA board with Virtex 6 and a 1GiB DDR memory and serve for further theoretical analysis of the system performance for various linear system sizes and the architecture of the system.

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10.1109/DSD.2013.125

Katedra počítačových systémů

Residual processor (RP) is a dedicated hardware for solution of sets of linear congruences. RPs are parts of a larger modular system for error-free solution of linear equations in residue arithmetic. We present new FPGA and ASIC RP implementations, focusing mainly on their memory units being a bottleneck of the calculation and therefore determining the efficiency of the system. First, we choose an FPGA to easily test the functionality of our implementation, then we do the same in ASIC, and finally we compare both implementations together. The experimental FPGA results are obtained for Xilinx Virtex 6, while the ASIC results are obtained from Synopsys tools with a 130 nm standard cell library. Results also present a maximum matrix dimension fitting directly into the FPGA and achieved speed as a function of the dimension.

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10.1109/ICECS.2012.6463632

Katedra počítačových systémů

The residual processor is a dedicated hardware for solving sets of linear congruences. It is a part of the modular system for solving sets of linear equations without rounding errors using Residue Number System. We present a new FPGA implementation of the residual processor, focusing mainly on the memory unit that forms a bottleneck of the calculation, and therefore determines the effectivity of the system. FPGA has been chosen, as it allows us to optimally implement the designed architecture depending on the size of the problem. The proposed memory architecture of the modular system is implemented using the internal FPGA block RAM. Experimental results are obtained for the Xilinx Virtex 6 family. Results present the maximum matrix dimension fitting directly into the FPGA, and achieved speed as a function of the dimension.

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10.1109/DSD.2011.42

Katedra číslicového návrhu

FPGAs are susceptible to many environment effects that can cause soft errors (errors which can be corrected by the reconfiguration ability of the FPGA). Two different fault models are discussed and compared in this paper. The first one - Stuck-at model - is widely used in many applications and it is not limited to the FPGAs. The second one - Bit-flip model - can affect SRAM cells that are used to configure the internal routing of the FPGA and to set up the behavior of the Look-Up Tables (LUTs). The change of the LUT behavior is the only Bit-flip effect considered in this paper. A fault model analysis has been performed on small example designs in order to find the differences between the fault models. This paper discusses the relevance of using two types of models Stuck-at and Bit-flip with respect to the dependability characteristics Fault Security (FS) and Self-Testing (ST). The fault simulation using both fault models has been performed to verify the analysis

Kapitola v knize

10.4018/978-1-60960-212-3

Katedra číslicového návrhu

The main aim of this chapter is to present the way, how to design fault-tolerant or fail-safe systems in programmable hardware (FPGAs) and therefore to use FPGAs in mission-critical applications, too. RAM based FPGAs are usually taken for unreliable due to high probability of transient faults (SEU) and therefore inapplicable in this area. But FPGAs can be easily reconfigured. Our aim is to utilize appropriate type of FPGA reconfiguration and to combine it with well-known methods for fail-safe and fault-tolerant design (duplex, TMR) including on-line testing methods for fault detection and then startup of the reconfiguration process. Dependability parameters' calculations based on reliability models is integral part of proposed methodology. The trade-off between the requested level of dependability characteristics of a designed system and area overhead with respect to FPGA possible faults is main property and advantage of proposed methodology.

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10.1109/DSD.2010.112

Katedra číslicového návrhu

A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to find Critical points - the places, where faults are difficult to detect. The partial duplication of the design with regard to these critical points is able to increase the faults coverage with a low area overhead cost. Due to higher fault coverage we can increase the dependability parameters. The proposed modification is tested on the railway station safety devices designs implemented in the FPGA.

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10.1109/DSD.2009.210

Katedra číslicového návrhu

The method how to design a safety device of railway station efficiently and scalable is proposed. The safety device for any configuration of railway station can be built from five basic blocks. These basic blocks are connected together with universal interface. Each block is based on a finite state machine. The finite state machines are "Moore" type. Each state machine is divided into three basic parts, where each part is designed as a self-checking circuit ensuring fault detection. Our methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed.